Diagnostic Test Generation and Fault Simulation Algorithms for Transition Faults∗

To distinguish between a pair of transition faults, we need to find a test vector pair that produces different output responses for the two faults. By adding a few logic gates and one modeling flip-flop to the circuit under test (CUT), we create a diagnostic ATPG model usable by a conventional stuck-at fault test generator. Given a transition fault pair, this ATPG model either finds a distinguishing test or proves the faults to be equivalent. An efficient fault simulator is devised to find undistinguished fault pairs from a fault list for a certain test vector set. The number of fault pairs that needs to be targeted by the ATPG is greatly reduced after diagnostic fault simulation. A fault that is distinguished from all other faults is dropped from further simulation, thus making the complexity of diagnostic fault simulation similar to conventional fault simulation. We use a previously proposed diagnostic coverage (DC) metric to determine the distinguishability (diagnosability) of a test vector set. Experimental results show improved DC for benchmark circuits after applying the proposed diagnostic ATPG algorithms.